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Senior SoC Integration and Performance Architect
Auburn Hills, United States
On-site
Role summary
Lead the analysis and optimization of system-level performance across heterogeneous multi-core architectures including CPUs, GPUs, and NPUs. This role ensures maximum resource utilization and eliminates system latencies through advanced modeling and simulation prior to physical silicon tape-out.
Details
LocationAuburn Hills, United States
Work typeOn-site
Responsibilities
- Analyze execution paths across multi-core CPUs, GPUs, and NPUs to eliminate system latencies and resource starvation
- Model and simulate performance constraints of next-gen applications prior to physical silicon tape-out
- Define hardware allocation profiles including core pinning, memory interleaving, and cache isolation
- Drive cross-functional optimization efforts to maximize SoC resource utilization across memory, CPU, and power
- Establish automated performance benchmarking pipelines for continuous integration
Requirements
Candidates must have a strong technical foundation in computer architecture and experience working with high-performance compute components. Practical knowledge of interconnect buses and profiling tools is essential for success in this role.
Experience
Minimum 8 years of experience in system-level architecture and SoC performance profiling.
Education
Master’s degree or higher in Computer Architecture, Electrical Engineering, or related field.
Growth opportunities
The role involves leading technical initiatives and mentoring junior engineers, offering a path toward senior technical leadership.
Team structure
Reports to the architecture department and leads cross-functional optimization efforts with other engineering teams.